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what's incremental synthesis ?
Aa far as I'm aware, incremental synthesis is vivado trying to build a new FPGA bitstream by modifying a snapshot of the previous build, to ostensibly save time. Because the SID FPGA implementation is a relatively small part of the MEGA65 core, it really likes to forget to add any changes I make, especially related to timing optimization (it took me so long to figure out it had re-enabled itself, after disabling it my total negative slack was cut in half due to it finally registering all the pipelining and other optimization). I've also had vivado outright lock up with some cases.
Just joking, I love that you explained further but to be honest I still have no idea what is going on, haha. The bit about "modifying a snapshot of the previous build" sounds like the idea behind binary diffing?
Ok, I looked up Vivado and now I have a better idea. A field very alien to me but fascinating to hear about
FPGAs are good fun, and some of the stuff I'm working on in particular gets even crazier. My current project is emulating a partially analog soundchip (the 6581 and 8580 SIDs) with 32 bit integers, because FPGAs can't do analog. The best part is, it actually (mostly) works. Still have coefficient issues with the RC circuits, and the Rf1 and Rf2 voltage-controlled resistor coefficient tables need to be recalculated, but it's already looking pretty good.
Good fun lol
Are you trying to replicate functionality from older hardware ?
Correct. Goal is to emulate the SIDs, and the filters are analog, so analog simulation is required.