this post was submitted on 17 Jan 2025
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Factorio
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In computing this sort of a problem would generally be solved by tagging via packet metadata - wouldn't it be simpler to reserve a portion of the signal for a recipient address for signal decoding?
That would be way easier. I'm a dumb.
I mean TDMA is also a perfectly valid solution.
Just needs an easier way to synchronize clocks. Maybe one (master) station could send out a sync word that lets all other stations start their clocks.
The easy solution to clock sync was to only have one clock. There's some funkiness required to TX a signal during the TX's clock cycle due to combinator timing but, I used that to my advantage on the RX side as it now only requires a single frame delay combinator to keep the signal alive 100% of the time.
I am a dev in my professional life - the number of times I've used that reply to feedback is innumerable (I literally used it on Wednesday in reply to a proposed solution to mitigating replication lag).
Realizing you did a dumb thing is part of the game of life. Now you've finished building one awesome system and can probably refactor it to an even awesomer system!
Woo! Same! I'm working on a bit packing solution ATM. Should be more UPS friendly and more resource friendly :D
I think I was leaning into the clock method as it doesn't have an upper/lower limit to circuit values or number of distinct circuits. Actually as I'm typing this I realized concurrent signals would have to share a 32 bit address space greatly limiting the min/max values. Two channels already limits me to 2^16-1 assuming I want a signed value.