486

I would advice against using SSDs for storage of media and such. Not only because of their higher price, but also because flash memory cells tend to fade over time, causing read speeds to decrease considerably over time. This is particularily the case for mostly read-only workloads. For each read operation the flash memory cell being read loses a bit of its charge. Eventually the margin for the controller to be able to read the data will be so small, that it takes the controller lots of read operations to figure out the correct data. In the worst case this can lead to the SSD controller being unable to read some data alltogether.

No, tmpfs is always located in virtual memory. Have a look at the kernel documentation for more information about tmpfs.

It is. It might end up on disk in swap, if you run low on memory (and have some sort of disk-based swap enabled), but usually it is located in RAM.

Try diasbling the second DHCP server altogether. You only need one, since you have a flat network.

Are you sure there is exactly one DHCP server running?

I'm exclusively running unprivileged LXC containers and haven't had any issues regarding the firewall, neither with iptables nor nftables.

No, it is not like Docker. You can treat an LXC container pretty much like a VM in most instances, including firewall rules. To answer the question, you can use fail2ban just like you had done in your VM, meaning you can run it inside the LXC container, where fail2ban can change the firewall rules of that container as it sees fit.

You could give bubblewrap a try instead. It is quite similar to systemd-nspawn.

I understood that. My point was rather that in this particular case (a CPU bug that could be fixed via microcode, but AMD chose not to do so for certain CPUs), RISC-V wouldn't have been of any advantage, because there would be nothing to fix in the first place. Sure, one could introduce microcode for RISC-V and people have argued in favor of doing so for this exact reason, but the architecture was intentionally designed to not require microcode.

As much as I like RISC-V, it is kind of ironic to suggest RISC-V ist the solution to this. At least as it stands, because of RISC-V's simplicity, most if not all current RISC-V CPUs don't even run microcode, so there is nothing to update/fix in case of a CPU bug. There's even a very current example of this problem with that chinese RISC-V cpu that has this "GhostWrite" bug that allows every unpriviliged process to gain root access.

That's good, I never liked the clunky .home.arpa domain.

Thanks for your notes on that part. Sometimes, when I didn't have a special temperature sensor part at hand, I have used a normal silicon diode as a temperature sensor. That works okay, but calibrating it is a little annoying, as it isn't exactly linear. For more serious projects, I usually use the DS18B20. I like that part because it is easy to use, no need for any calibration, since the D/A conversion happens internally in the component and you talk to it digitally.