this post was submitted on 23 Jun 2024
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[–] [email protected] 142 points 5 days ago* (last edited 5 days ago) (20 children)

We do, depending on how you count it.

There's two major widths in a processor. The data register width and the address bus width, but even that is not the whole story. If you go back to a processor like the 68000, the classic 16-bit processor, it has:

  • 32-bit data registers
  • 16- bit ALU
  • 16-bit data bus
  • 32-bit address registers
  • 24-bit address bus

Some people called it a 16/32 bit processor, but really it was the 16-bit ALU that classified it as 16-bits.

If you look at a Zen 4 core it has:

  • 64-bit data registers
  • 512-bit AVX data registers
  • 6 x 64-bit integer ALUs
  • 4 x 256-bit AVX ALUs
  • 2 x 128-bit data bus to DDR5 (dual edge 64-bit)
  • ~40-bits of addressable physical RAM

So, what do you want to call this processor?

64-bit (integer width), 128-bit (physical data bus width), 256-bit (widest ALU) or 512-bit (widest register width)? Do you want to multiply those numbers up by the number of ALUs in a core? ...by the number of cores on a piece of silicon?

Me, I'd say Zen4 was a 256-bit core, but you could argue any of the above numbers.

Basically, it's a measurement that lost all meaning so people stopped using it.

[–] Buffalox 13 points 4 days ago* (last edited 4 days ago) (2 children)

At less than a tenth the size, this is actually a better explanation than the article. Already correcting the fact that we do at the very beginning.
If you absolutely had to put a bit width on the Zen 4, the 2x128 bit data bus is probably the best single measure totaling 256 bit IMO.

[–] [email protected] 3 points 4 days ago (1 children)

Even then, at what point do you measure it? DDR interface is likely very much narrower than the interfaces between cache levels. Where does the core end and the memory begin?

[–] Buffalox 4 points 4 days ago

Yes you are 100% right, and I did consider level 3 cache as a better measure, because that allows communication between cores without the need to go through RAM, and cache generally has a high hit rate. But this number was surprisingly difficult to find, so I settled on the data bus.
Anyways it would be absolutely fair to call it 256bit by more than one measure. But for sure it isn't just 64 bit, because it has 512 bit instructions, so the instruction set isn't limited to 64 bit. Even if someone was stubborn enough to claim the general instruction set is 64 bit, it has the ability to decode and execute 2 simultaneous 64 bit instructions per core, making at least 128 bit by any measure.

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