this post was submitted on 07 Mar 2024
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Yeah. RISC-V has been the goal. But, I was hoping for something a bit simpler and easier to get a hold of as a bare chip (would be nice if a 6502 or similar could do it). That way, I'd be able to reduce the complexity and scope. I suppose I could use a soft core on an FPGA. Not confident on my gateware skills yet to be certain that I wouldn't waste time debugging something caused by my own faulty HDL or bitstream.
I have found low-cost Sophgo chips (SG2000 - RISC-V, mostly) but last time I checked they didn't have mainline support due to problems in the C910 cores not properly implementing IEEE-754 FPUs and the vector extension predating the RVV1.0 release. If the upcoming Sophgo SG2380 becomes similarly availabile, that might do it as they licensed cores from Si-Five that should be fully compliant with the ISA spec.