RISC-V

https://wiki.debian.org/RISC-V

https://blog.aurel32.net/welcome-debian-riscv64.html

BeagleBoard has launched a new single-board computer called the BeagleV-Ahead. It’s the same shape as the company’s BeagleBone Black and it’s compatible with some accessories designed for that board.

But instead of an ARM-based processor, the new BeagleV-Ahead is powered by a quad-core RISC-V processor. The new board is available now for around $149.

At the heart of the new board is an Alibaba T-Head TH1520 chip which features four 2 GHz Xuantie C910 CPU cores, Imagination BXM-4-64 integrated graphics and a neural processing unit with up to 4 TOPS of AI performance.

Abstract—Microarchitectural attacks threaten the security of computer systems even in the absence of software vulnerabil- ities. Such attacks are well explored on x86 and ARM CPUs, with a wide range of proposed but not-yet deployed hardware countermeasures. With the standardization of the RISC-V instruction set architecture and the announcement of support for the architecture by major processor vendors, RISC-V CPUs are on the verge of becoming ubiquitous. However, the microarchitectural attack surface of the first commercially- available RISC-V hardware CPUs still needs to be explored. This paper analyzes the two commercially-available off-the- shelf 64-bit RISC-V (hardware) CPUs used in most RISC-V systems running a full-fledged commodity Linux system. We evaluate the microarchitectural attack surface and introduce 3 new microarchitectural attack techniques: Cache+Time, a novel cache-line-granular cache attack without shared memory, Flush+Fault exploiting the Harvard cache architecture for Flush+Reload, and CycleDrift exploiting unprivileged access to instruction-retirement information. We also show that many known attacks apply to these RISC-V CPUs, mainly due to non-existing hardware countermeasures and instruction-set subtleties that do not consider the microarchitectural attack surface. We demonstrate our attacks in 6 case studies, includ- ing the first RISC-V-specific microarchitectural KASLR break and a CycleDrift-based method for detecting kernel activity. Based on our analysis, we stress the need to consider the microarchitectural attack surface during every step of a CPU design, including custom ISA extensions.

Launched with only an 8GB RAM and 8GB eMMC configuration ($119), this SBC is now available in 8and32GB ($135) and 16and128GB ($179) configurations.

CPU: 
    RISC-V 64GCV (but note the vector extension is v 0.7.1 draft) C910 x4 (up to 2.0GHz); 4TOPS@INT8 NPU (up to 1GHz) 
GPU: 
    OpenGL ES3.0/3.1/3.2, OpenCL 1.1/1.2/2.0, Vulkan 1.1/1.2, 50.7GFLOPS
Memory/Storage: 
    Up to 16GB LPDDR4
    Up to 128 GB eMMC
    1x MicroSD card slot
Display:
    1x HDMI 2.0 (4K@60fps)
    4-lane MIPI DSI (4K@50fps)
Audio:
    3.5mm Audio jack
    Stereo Speaker, PDM MIC
Camera:
    1x 4-lane MIPI CSI + 1×2-lane MIPI CSI (up to 4K@30fps)
Connectivity:
    2x Gigabit Ethernet RJ45 (optional PoE)
    WiFi4 + BT5 or WiFi6 + BT5
    1x Antenna connector
I/O Interface:
    2x10-Pin GPIO expansion header
USB:
    4x USB 3.0 Type-A
    1x USB2.0 Type-C
Power: 
    12V/2A DC, or USB Type-C, or PoE
OS:
    Debian
    OpenWRT
    Android
Operating Temperature:
    -20°C to 60°C
Mechanical: 
    85 x 103mm

Video explanation: https://youtu.be/zXPiqk0-zDY

MangoPi is working on the first RISC-V router I’ve seen, based on the ArtInChip D213ECV 64-bit RISC-V processor with 256MB SPI NAND flash, two Gigabit Ethernet ports, two USB 2.0 ports, MIPI DSI+touch connector, support for CAN Bus and RS485, and expansion through a 22-pin GPIO header.

$1199 for the board with chip+heatsink, or $1999 for a complete assembled system. Delivery by Christmas 2023.

I don't know, it's great to see the form factor, but I don't think twice the price of the HiFive Unmatched for 64 T-Head C920 cores (about RaspBi 3B+ level with RVV 0.71 draft extension) glued together is worth it.

I'll keep watching for Horse Creek and whatever Ventana Micro Systems are doing.

What do you all think?

Can't get currently a cooler for the CPU and GPU and wonder if it regulates itself to not melt down or destroy itself.

semiwiki comments

The project's own website: https://mikrophone.net

Not mine, I just found it on YouTube.

Last week Starfive released the June release of their Debian Linux version which fixed a number of bugs and added some welcome new programs.

cross-posted from: https://sopuli.xyz/post/623623

Linux foundation and a number of big names in tech commit top talent and invest on RISC-V. The companies that support this initiative are, among others, Google, Intel, MediaTek, Nvidia, Qualcomm, Red Hat, Samsung, SiFive, etc.

I think it's fine that rvv 0.7.1 isn't included in the official toolchains anymore.

As fun as it is to play around with rvv on those chips, I see those as development devices and no normal user should enable the vector extension there anyways.

I'd also rather the clang team puts some work into finally eliminating redundant vscale load/stores (this is THE thing that's stopping rvv ports for things like SIMDe), then adding rvv 0.7.1 support.

on r/RISCV