RISC-V

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RISC-V (pronounced "risk-five") is a license-free, modular, extensible instruction set architecture (ISA).

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MILLIONS of early RISCV CPUs ship with an INCOMPATIBLE VECTOR extensions probably nobody will use! (m.youtube.com)

submitted 1 year ago by [email protected] to c/[email protected]

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I think it's fine that rvv 0.7.1 isn't included in the official toolchains anymore.

As fun as it is to play around with rvv on those chips, I see those as development devices and no normal user should enable the vector extension there anyways.

I'd also rather the clang team puts some work into finally eliminating redundant vscale load/stores (this is THE thing that's stopping rvv ports for things like SIMDe), then adding rvv 0.7.1 support.

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